1:n2 MOS cascode circuits and their applications

Koichi Tanno*, Okihiko Ishizuka, Zheng Tang

*この論文の責任著者

研究成果: ジャーナルへの寄稿学術論文査読

4 被引用数 (Scopus)

抄録

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1:n2 for the N-type MOS cascode circuit and n2:1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits are confirmed by SPICE simulation with MOSIS 1.2 μm CMOS process parameters.

本文言語英語
ページ(範囲)2159-2165
ページ数7
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E79-A
12
出版ステータス出版済み - 1996

ASJC Scopus 主題領域

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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