1:n2 MOS cascode circuits and their applications

Koichi Tanno*, Okihiko Ishizuka, Zheng Tang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1:n2 for the N-type MOS cascode circuit and n2:1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits are confirmed by SPICE simulation with MOSIS 1.2 μm CMOS process parameters.

Original languageEnglish
Pages (from-to)2159-2165
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE79-A
Issue number12
StatePublished - 1996

Keywords

  • Circuit theory and design
  • Integrated circuit
  • MOS LSI
  • MOS analog circuit
  • Threshold voltage

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Fingerprint

Dive into the research topics of '1:n2 MOS cascode circuits and their applications'. Together they form a unique fingerprint.

Cite this