Clock-feedthrough compensated digital-to-analog converters

Hiroki Matsumoto; Zheng Tang; Okihiko Ishizuka

Clock-feedthrough compensated digital-to-analog converters

Hiroki Matsumoto^*, Zheng Tang, Okihiko Ishizuka

^*Corresponding author for this work

Intellectual Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Switched-capacitor (SC) digital-to-analog (D/A) converters which are insensitive to clock-feedthrough charge caused by MOS analog switches, offset- and gain-error of unity gain buffers (UGB) are presented. Because their configurations are based on UGB, the conversion rate is estimated to 90 Mb/s. Resolution of the proposed converter is limited by top plate parasitic capacitance and can be reached till 9 bit.

Original language	English
Title of host publication	Midwest Symposium on Circuits and Systems
Publisher	Publ by IEEE
Pages	744-747
Number of pages	4
ISBN (Print)	0780300815
State	Published - 1991
Event	33rd Midwest Symposium on Circuits and Systems - Calgary, Alberta, Can Duration: 1990/08/12 → 1990/08/15

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2

Conference

Conference	33rd Midwest Symposium on Circuits and Systems
City	Calgary, Alberta, Can
Period	1990/08/12 → 1990/08/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@inproceedings{10477c2b5ab9464194e041a1f7d3ceaa,

title = "Clock-feedthrough compensated digital-to-analog converters",

abstract = "Switched-capacitor (SC) digital-to-analog (D/A) converters which are insensitive to clock-feedthrough charge caused by MOS analog switches, offset- and gain-error of unity gain buffers (UGB) are presented. Because their configurations are based on UGB, the conversion rate is estimated to 90 Mb/s. Resolution of the proposed converter is limited by top plate parasitic capacitance and can be reached till 9 bit.",

author = "Hiroki Matsumoto and Zheng Tang and Okihiko Ishizuka",

year = "1991",

language = "英語",

isbn = "0780300815",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Publ by IEEE",

pages = "744--747",

booktitle = "Midwest Symposium on Circuits and Systems",

note = "33rd Midwest Symposium on Circuits and Systems ; Conference date: 12-08-1990 Through 15-08-1990",

}

TY - GEN

T1 - Clock-feedthrough compensated digital-to-analog converters

AU - Matsumoto, Hiroki

AU - Tang, Zheng

AU - Ishizuka, Okihiko

PY - 1991

Y1 - 1991

N2 - Switched-capacitor (SC) digital-to-analog (D/A) converters which are insensitive to clock-feedthrough charge caused by MOS analog switches, offset- and gain-error of unity gain buffers (UGB) are presented. Because their configurations are based on UGB, the conversion rate is estimated to 90 Mb/s. Resolution of the proposed converter is limited by top plate parasitic capacitance and can be reached till 9 bit.

AB - Switched-capacitor (SC) digital-to-analog (D/A) converters which are insensitive to clock-feedthrough charge caused by MOS analog switches, offset- and gain-error of unity gain buffers (UGB) are presented. Because their configurations are based on UGB, the conversion rate is estimated to 90 Mb/s. Resolution of the proposed converter is limited by top plate parasitic capacitance and can be reached till 9 bit.

UR - http://www.scopus.com/inward/record.url?scp=0026390990&partnerID=8YFLogxK

M3 - 会議への寄与

AN - SCOPUS:0026390990

SN - 0780300815

T3 - Midwest Symposium on Circuits and Systems

SP - 744

EP - 747

BT - Midwest Symposium on Circuits and Systems

PB - Publ by IEEE

T2 - 33rd Midwest Symposium on Circuits and Systems

Y2 - 12 August 1990 through 15 August 1990

ER -

Clock-feedthrough compensated digital-to-analog converters

Abstract

Publication series

Conference

ASJC Scopus subject areas

Fingerprint

Cite this