A 1-V, 1-Vp-p input range, four-quadrant analog multiplier using neuron-MOS transistors

Koichi Tanno*, Okihiko Ishizuka, Zheng Tang

*この論文の責任著者

研究成果: ジャーナルへの寄稿学術論文査読

抄録

In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2. 0 m CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0. 77% and a total harmonic distortion of 0. 62% are obtained with fullscale input conditions. The maximum power consumption and -3 dB bandwidth are 9. 56/zW and 107 MHz, respectively. The active area of the proposed multiplier is 210 /im x 140 ftm.

本文言語英語
ページ(範囲)750-757
ページ数8
ジャーナルIEICE Transactions on Electronics
E82-C
5
出版ステータス出版済み - 1999

ASJC Scopus 主題領域

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

フィンガープリント

「A 1-V, 1-Vp-p input range, four-quadrant analog multiplier using neuron-MOS transistors」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル