VLSI design of a quaternary multiplier with direct generation of partial products

This paper presents the VLSI design of a novel quaternary multiplier with direct generation of partial products using a radix-4 redundant number system. The structure of the multiplier is so simple and regular that it is suitable for VLSI implementation. Partial products in the multiplier are generated as the corresponding value 0 to 9 and are implemented by simple CMOS current-mode circuits. To add partial products in the multiplier, we introduce a redundant multi-valued adder (RMA). The RMA can add two redundant numbers in the final level of additions are also redundant. We use a high speed quaternary carry-look-ahead adder (QCLA) to convert a redundant number into a non-redundant number. The chip of a CMOS 4×4-digit quaternary multiplier is fabricated in cooperation with the VLSI Design and Education Center of Tokyo University, Japan. The chip and core sizes of the multiplier are 2.3×2.3mm² and 1.5×1.6mm², respectively, with 1.5μm technology. The layout design of a 16×16-digit quaternary multiplier with 0.8μm technology is also discussed for the practical use.