Self-alignment a-Si FET by using a lift-off technique

H. Okada; Y. Uchida; Y. Watanabe; M. Matsumura

doi:10.1049/el:19850448

Self-alignment a-Si FET by using a lift-off technique

H. Okada, Y. Uchida, Y. Watanabe, M. Matsumura

Electric and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

New self-alignment amorphous-silicon field-effect transistors (a-Si FETs) have been proposed and demonstrated. This method uses lift-off and ion-implantation techniques, and no voltage offset was observed. Simple analysis indicates that this structure may be used to produce devices with channel lengths down to 5 μm.

Original language	English
Pages (from-to)	633-634
Number of pages	2
Journal	Electronics Letters
Volume	21
Issue number	15
DOIs	https://doi.org/10.1049/el:19850448
State	Published - 1985/07/18

Keywords

Fieldeffect transistors
Semiconductor devices and materials

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19850448

Cite this

@article{2deaaaf79e314e27a571a2c65a7f44f1,

title = "Self-alignment a-Si FET by using a lift-off technique",

abstract = "New self-alignment amorphous-silicon field-effect transistors (a-Si FETs) have been proposed and demonstrated. This method uses lift-off and ion-implantation techniques, and no voltage offset was observed. Simple analysis indicates that this structure may be used to produce devices with channel lengths down to 5 μm.",

keywords = "Fieldeffect transistors, Semiconductor devices and materials",

author = "H. Okada and Y. Uchida and Y. Watanabe and M. Matsumura",

year = "1985",

month = jul,

day = "18",

doi = "10.1049/el:19850448",

language = "英語",

volume = "21",

pages = "633--634",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley & Sons Inc.",

number = "15",

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T1 - Self-alignment a-Si FET by using a lift-off technique

AU - Okada, H.

AU - Uchida, Y.

AU - Watanabe, Y.

AU - Matsumura, M.

PY - 1985/7/18

Y1 - 1985/7/18

N2 - New self-alignment amorphous-silicon field-effect transistors (a-Si FETs) have been proposed and demonstrated. This method uses lift-off and ion-implantation techniques, and no voltage offset was observed. Simple analysis indicates that this structure may be used to produce devices with channel lengths down to 5 μm.

AB - New self-alignment amorphous-silicon field-effect transistors (a-Si FETs) have been proposed and demonstrated. This method uses lift-off and ion-implantation techniques, and no voltage offset was observed. Simple analysis indicates that this structure may be used to produce devices with channel lengths down to 5 μm.

KW - Fieldeffect transistors

KW - Semiconductor devices and materials

UR - http://www.scopus.com/inward/record.url?scp=0022097648&partnerID=8YFLogxK

U2 - 10.1049/el:19850448

DO - 10.1049/el:19850448

M3 - 学術論文

AN - SCOPUS:0022097648

SN - 0013-5194

VL - 21

SP - 633

EP - 634

JO - Electronics Letters

JF - Electronics Letters

IS - 15

ER -

Self-alignment a-Si FET by using a lift-off technique

Abstract

Keywords

ASJC Scopus subject areas

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